The present invention generally relates to master slice type semiconductor integrated circuits, and more particularly to a master slice type semiconductor integrated circuit having a sea of gates.
Generally, in a master slice type semiconductor integrated circuit, a plurality of columns of basic cells are arranged with interconnection (wiring) channels sandwiched therebetween at a central portion of a chip excluding regions of input/ output cells. But in the recent master slice type semiconductor integrated circuit having the so-called sea of gates (or channel-less gate array), the basic cells are arranged in the entire central portion of the chip excluding the regions of the input/output cells, and logic unit cells and the interconnection channels are formed on the basic cells. According to this master slice type semiconductor integrated circuit having the sea of gates, it is possible to integrate a large number of gates because the interconnection channels can be reduced to a minimum.
When the integration density of the master slice type semiconductor integrated circuit increases by the use of the sea of gates, the circuit construction generally requires in addition to the logic unit cells random access memories (RAMs), read only memories (ROMs) and the like. For this reason, it is desirable that the master slice type semiconductor integrated circuit having the sea of gates has such a construction that the RAMs, ROMs and the like can be formed with ease from the basic cells in addition to the formation of the logic unit cells.
In the conventional master slice type semiconductor integrated circuit having the sea of gates, the basic cells are basically formed in a complementary metal oxide semiconductor (CMOS) structure for the formation of the logic unit cells. In other words, the basic cells are made of the same number of N-channel MOS transistors and P-channel MOS transistors.
FIG. 1 shows an example of the static RAM formed in the conventional master slice type semiconductor integrated circuit having the sea of gates. As shown, a latch circuit is constituted by N-channel MOS transistors N1 and N2 and P-channel MOS transistors P1 and P2, and a transmission gate is constituted by N-channel MOS transistors N3 and N4. WL denotes a word line, and BL and XBL denote bit lines. The numbers of N-channel MOS transistors and P-channel MOS transistors used in the static RAM are not the same. As a result, the utilization efficiency of the basic cells is poor when forming the static RAM in the semiconductor integrated circuit having the sea of gates.
In addition, when forming the ROM in the conventional master slice type semiconductor integrated circuit having the sea of gates, only N-channel MOS transistors are generally used with priority on the read-out speed of the ROM. In this case, only one-half portion of the basic cells, that is, only the N-channel MOS transistors, are used, thereby resulting in a poor utilization efficiency of the basic cells.
On the other hand, when the integration density of the master slice type semiconductor integrated circuit increases by the use of the sea of gates, there is a demand to integrate a programmable logic array (PLA) in the circuit in addition to the logic unit cells. The PLA has a two-level structure comprising ROMs in an AND plane and ROMs in an OR plane, and it is possible to generate various kinds of logic functions by use of a small number of transistors.
FIG. 2 shows an example of the conventional PLA. Input signals A.sub.i and B.sub.i are applied to terminals 1a and 1b. Signals A.sub.i, A.sub.i, B.sub.i and B.sub.i are supplied to input lines 3a, 3b, 4a and 4b, respectively. N-channel MOS transistors of an AND plane 6 are provided at intersections of the input lines 3a, 3b, 4a and 4b and product term lines 5a, 5b, 5c and 5d. In addition N-channel MOS transistors of an OR plane 8 are provided at intersections of the product term lines 5a, 5b, 5c and 5d and output lines 7a and 7b. Output signals Z.sub.1 and Z.sub.2 are output from terminals 2a and 2b. The programming is carried out by connecting drains of the N-channel MOS transistors of the AND plane 6 to the respective product term lines 5a through 5d and connecting drains of the N-channels MOS transistors of the OR plane 8 to the respective output lines 7a and 7b at positions encircled by phantom lines. V.sub.DD denotes a power source voltage, and .phi..sub.1 and .phi..sub.2 denote clock signals of mutually different phases.
However, the following problems occur when an attempt is made to form the PLA in the conventional master slice type semiconductor integrated circuit.
First, only N-channel MOS transistors are used on the AND plane 6 and the OR plane 8 with priority on the read-out speed, but in the conventional semiconductor integrated circuit having the sea of gates, the basic cells are basically formed in the CMOS structure for the formation of the logic unit cells. In other words, the basic cells are made of the same number of N-channel MOS transistors and P-channel MOS transistors. For this reason, when the PLA is formed by use of only the N-channel MOS transistors, the P-channel MOS transistors of the basic cells will not be used, and the utilization efficiency of the basic cells becomes poor.
Second, in the conventional master slice type semiconductor integrated circuit, a plurality of transistors are arranged in an X-direction (column direction) within the basic cell, for example, and gates thereof are connected in common. On the other hand, in the PLA, gates of the plurality of transistors arranged in the column direction or the AND plane 6 are connected in common, and gates of the plurality of transistors arranged in a row direction on the OR plane 8 are connected in common. Accordingly, when the input lines 3a through 4b are provided in the X-direction (column direction) of the basic cells of the semiconductor integrated circuit and the product term lines 5a through 5d are provided in a Y-direction (row direction) of the basic cells, only a single transistor of the basic cell can be used on the OR plane 8, thereby deteriorating the utilization efficiency of the basic cells.
For these reasons, the PLA is not formed in the conventional master slice type semiconductor integrated circuit.